ADC1453D开发板套件编程器的评估板-模数转换器（ADC）规格书PDF中文资料

1. General description

The ADC1453D is a dual channel 14-bit Analog-to-Digital Converter (ADC) with

JESD204B interface (which is backward compatible with the JESD204A interface)

optimized for high dynamic performance and low power consumption at sample rates up

to 246 Msps. Pipelined architecture and output error correction guarantee zero missing

codes over the entire operating range.

The ADC1453D has JESD204B serial outputs over a configurable number of lanes (1 or

2). Multiple Device Synchronization (MDS) allows sample-accurate synchronization of the

data outputs of multiple ADC devices. It guarantees a maximum skew of one clock period

between as many as 16 output lanes from up to eight ADC1453D devices.

An integrated Serial Peripheral Interface (SPI) allows easy configuration of the ADC. The

device also includes a programmable full-scale to allow a flexible input voltage range of

1 V (p-p) to 2 V (p-p).

The ADC1453D is available in an VFQFPN56 package (8 mm  8 mm outline). It is

supported with customer demo boards.

2. Features and benefits

 Dual channel 14-bit resolution ADC  SNR = 70.1 dBFS; fs = 246 Msps;

fi = 190 MHz

 Sampling rate up to 246 Msps  SFDR = 80 dBc; fs = 246 Msps;

fi

= 190 MHz

 JESD204B Device Subclass 0, 1 and 2

with harmonic clocking and deterministic

latency support

 IMD3 = 86 dBc; fs = 246 Msps;

fi1 = 188.5 MHz; fi2 = 191.5 MHz

 ADC Multiple Device Synchronization

(MDS)

 Analog input bandwidth of 1 GHz

(typical)

 Offset binary, two’s complement and

Gray output data

 Pin to pin compatible with ADC1413D

and ADC1443D series

 Two JESD204B serial output lanes, up

to 5 Gbps

 Typical power dissipation = 1.4 W;

fs = 246 Msps

 Flexible input voltage range from

1 V (p-p) to 2 V (p-p) by 1 dB steps

 Industrial temperature range from

40 C to +85 C

 Clock input divider from 1 to 8 supports

harmonic clocking

 Serial Peripheral Interface (SPI) for

configuration control and status

monitoring

 Duty Cycle Stabilizer (DCS)  VFQFPN56 package; 8  8 mm