ADC12QJ800数据手册TI中文资料规格书

描述 Description

ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3 dB) of 6 GHz enables direct RF sampling of of L-band and S-band.

特性 Features

• ADC Core:
• Resolution: 12 Bit
• Maximum sampling rate: 800 MSPS
• Non-interleaved architecture
• Internal dither reduces high-order harmonics

• Performance specifications (–1 dBFS):
• SNR (97 MHz): 57.6 dBFS
• ENOB (97 MHz): 9.0 Bits
• SFDR (97 MHz): 62 dBFS
• Noise floor (–20 dBFS): –146.1 dBFS/Hz

• Full-scale input voltage: 800 mVPP-DIFF
• Full-power input bandwidth: 6 GHz
• JESD204C Serial data interface:
• Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
• Maximum baud-rate: 17.16 Gbps
• 64B/66B and 8B/10B encoding modes
• Subclass-1 support for deterministic latency
• Compatible with JESD204B receivers

• Optional internal sampling clock generation
• Internal PLL and VCO (7.2–8.2 GHz)

• SYSREF Windowing eases synchronization
• Four clock outputs simplify system clocking
• Reference clocks for FPGA or adjacent ADC
• Reference clock for SerDes transceivers

• Timestamp input and output for pulsed systems
• Power consumption (800 MSPS):
• Quad Channel: 415 mW / channel
• Dual channel: 555 mW / channel
• Single channel: 830 mW

• Power supplies: 1.1 V, 1.9 V