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ADC12QJ1600-SEP中文资料PDF规格书
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1 Features
• Radiation Tolerance:
– Total Ionizing Dose (TID): 30 krad (Si)
– Single Event Latchup (SEL): 43 MeV-cm2/mg
– Single Event Upset (SEU) immune registers
• Space-enhanced plastic (space EP):
– Meets ASTM E595 outgassing specification
– Vendor item drawing (VID) V62/22610
– Temperature range: –55°C to 125°C
– One fabrication, assembly, and test site
– Wafer lot traceability
– Extended product life cycle
– Extended product change notification
• ADC Core:
– Resolution: 12 Bit
– Maximum sampling rate: 1.6 GSPS
– Non-interleaved architecture
– Internal dither reduces high-order harmonics
• Performance specifications (–1 dBFS):
– SNR (100 MHz): 57.4 dBFS
– ENOB (100 MHz): 9.1 Bits
– SFDR (100 MHz): 64 dBc
– Noise floor (–20 dBFS): –147 dBFS
• Full-scale input voltage: 800 mVPP-DIFF
• Full-power input bandwidth: 6 GHz
• JESD204C Serial data interface:
– Support for 2 to 8 total SerDes lanes
– Maximum baud-rate: 17.16 Gbps
– 64B/66B and 8B/10B encoding modes
– Subclass-1 support for deterministic latency
– Compatible with JESD204B receivers
• Optional internal sampling clock generation
– Internal PLL and VCO (7.2–8.2 GHz)
• SYSREF Windowing eases synchronization
• Four clock outputs simplify system clocking
– Reference clocks for FPGA or adjacent ADC
– Reference clock for SerDes transceivers
• Timestamp input and output for pulsed systems
• Power consumption (1 GSPS): 1.9 W
• Power supplies: 1.1 V, 1.9 V
2 Applications
• Electronic warfare (SIGINT, ELINT)
• Satellite communications (SATCOM)
3 Description
ADC12QJ1600-SEP is a quad channel, 12-bit, 1.6
GSPS analog-to-digital converters (ADC). Low power
consumption, high sampling rate and 12-bit resolution
makes the device suited for a variety of mulch-chanel
communications systems.
Full-power input bandwidth (-3 dB) of 6 GHz enables
direct RF sampling of L-band and S-band.
A number of clocking features are included to relax
system hardware requirements, such as an internal
phase-locked loop (PLL) with integrated voltagecontrolled
oscillator (VCO) to generate the sampling
clock. Four clock outputs are provided to clock the
logic and SerDes of the FPGA or ASIC. A timestamp
input and output is provided for pulsed systems.
JESD204C serialized interface decreases system size
by reducing the amount of printed circuit board (PCB)
routing. Interface modes support from 2 to 8 lanes
(dual and quad channel devices) or 1 to 4 lanes (for
the single channel device), with SerDes baud-rates up
to 17.16 Gbps, to allow the optimal configuration for
each application.
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
NATIONALSEMICONDUCTOR |
2020+ |
NA |
80000 |
只做自己库存,全新原装进口正品假一赔百,可开13%增 |
询价 | ||
AD |
02+ |
6 |
询价 | ||||
ADC12QM |
1 |
1 |
询价 | ||||
TI |
WQFN|60 |
70230 |
16余年资质 绝对原盒原盘 更多数量 |
询价 | |||
NS |
2402+ |
LLP-60 |
8324 |
原装正品!实单价优! |
询价 | ||
ADI/亚德诺 |
22+ |
66900 |
原封装 |
询价 | |||
NS/TI |
22+ |
60-LLP-EP |
10000 |
原装正品优势现货供应 |
询价 | ||
TI/德州仪器 |
22+ |
QFN |
9600 |
原装现货,优势供应,支持实单! |
询价 | ||
TexasInstruments |
18+ |
ICADC12BITQUADLVDS60-LLP |
6580 |
公司原装现货/欢迎来电咨询! |
询价 | ||
TI |
三年内 |
1983 |
纳立只做原装正品13590203865 |
询价 |