ADC128S102QML-SP数据手册TI中文资料规格书

描述 Description

The ADC128S102 device is a low-power, eight-channel CMOS 12-bit analog-to-digital converter specified for conversion throughput rates of 50 kSPS to 1 MSPS. The converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. The device can be configured to accept up to eight input signals at inputs IN0 through IN7.

The output serial data is straight binary and is compatible with several standards, such as SPI, QSPI, MICROWIRE, and many common DSP serial interfaces.

The ADC128S102 may be operated with independent analog and digital supplies. The analog supply (VA) can range from 2.7 V to 5.25 V, and the digital supply (VD) can range from 2.7 V to VA. Normal power consumption using a 3-V or 5-V supply is 2.3 mW and 10.7 mW, respectively. The power-down feature reduces the power consumption to 0.06 µW using a 3-V supply and 0.25 µW using a 5-V supply.

特性 Features

• 5962R07227
• Total Ionizing Dose 100 krad(Si)
• Single Event Latch-Up Immune 120 MeV-cm2/mg
• Single Event Functional Interrupt Immune 120 MeV-cm2/mg (See Radiation Report)

• Eight Input Channels
• Variable Power Management
• Independent Analog and Digital Supplies
• SPI™/QSPI™/MICROWIRE™/DSP Compatible
• Packaged in 16-Lead Ceramic SOIC
• Key Specifications
• Conversion Rate: 50 kSPS to 1 MSPS
• DNL (VA = VD = 5 V): +1.5 / −0.9 LSB (Maximum)
• INL (VA = VD = 5 V): +1.4 / −1.25 LSB (Maximum)
• Power Consumption
• 3-V Supply: 2.3 mW (Typical)
• 5-V Supply: 10.7 mW (Typical)