ADC10040-Q1中文资料10 位 40MSPS 数模转换器 (ADC) - 符合汽车应用标准数据手册TI规格书

描述 Description

The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW. The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement. The ADC10040Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 3 Qualified. This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.

特性 Features

• Single +3.0V Operation
• 400 MHz −3 dB Input Bandwidth
• Standby Mode
• Offset Binary or Two’s Complement Data Format
• AEC-Q100 Grade 3 Qualified
• Resolution: 10 Bits
• Full Power Bandwidth: 400 MHz
• SNR (fIN = 11 MHz): 59.6 dB (typ)
• Power Consumption, 40 MHz: 55.5 mW