丝印：ADC08DL502CIVV；Package：LQFP；Low Power, 8-Bit, Dual 500 MSPS A/D Converter

1FEATURES 2• Single +1.9V ±0.1V Operation • Duty Cycle Corrected Sample Clock KEY SPECIFICATIONS • Resolution: 8 Bits • Max Conversion Rate: 500 MSPS • Code Error Rate: 10−18 (typ) • ENOB @ 125 MHz Input: 7.5 Bits (typ) • DNL: ±0.15 LSB (typ) • Power Consumption – Operating in 1:2 Demu

文件：784.28 Kbytes 页数：53 Pages

TI2

德州仪器

丝印：ADC08DL502CIVV；Package：LQFP；Low Power, 8-Bit, Dual 500 MSPS A/D Converter

1FEATURES 2• Single +1.9V ±0.1V Operation • Duty Cycle Corrected Sample Clock KEY SPECIFICATIONS • Resolution: 8 Bits • Max Conversion Rate: 500 MSPS • Code Error Rate: 10−18 (typ) • ENOB @ 125 MHz Input: 7.5 Bits (typ) • DNL: ±0.15 LSB (typ) • Power Consumption – Operating in 1:2 Demu

文件：784.28 Kbytes 页数：53 Pages

TI2

德州仪器

丝印：ADC08DL502CIVV；Package：LQFP；Low Power, 8-Bit, Dual 500 MSPS A/D Converter

1FEATURES 2• Single +1.9V ±0.1V Operation • Duty Cycle Corrected Sample Clock KEY SPECIFICATIONS • Resolution: 8 Bits • Max Conversion Rate: 500 MSPS • Code Error Rate: 10−18 (typ) • ENOB @ 125 MHz Input: 7.5 Bits (typ) • DNL: ±0.15 LSB (typ) • Power Consumption – Operating in 1:2 Demu

文件：784.28 Kbytes 页数：53 Pages

TI2

德州仪器

丝印：ADC08DL502CIVV；Package：LQFP；Low Power, 8-Bit, Dual 500 MSPS A/D Converter

1FEATURES 2• Single +1.9V ±0.1V Operation • Duty Cycle Corrected Sample Clock KEY SPECIFICATIONS • Resolution: 8 Bits • Max Conversion Rate: 500 MSPS • Code Error Rate: 10−18 (typ) • ENOB @ 125 MHz Input: 7.5 Bits (typ) • DNL: ±0.15 LSB (typ) • Power Consumption – Operating in 1:2 Demu

文件：784.28 Kbytes 页数：53 Pages

TI2

德州仪器

Low Power, 8-Bit, Dual 500 MSPS A/D Converter

文件：1.13665 Mbytes 页数：43 Pages

TI1

德州仪器

Low Power, 8-Bit, Dual 500 MSPS A/D Converter

文件：1.13665 Mbytes 页数：43 Pages

TI1

德州仪器