ADC08D500数据手册集成电路（IC）的模数转换器（ADC）规格书PDF

描述 Description

The ADC08D500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V. Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate. The two converters can be interleaved and used as a single 1 GSPS ADC. The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

特性 Features

• Internal Sample-and-Hold
• Single +1.9V ±0.1V Operation
• Choice of SDR or DDR Output Clocking
• Interleave Mode for 2x Sampling Rate
• Multiple ADC Synchronization Capability
• Ensured No Missing Codes
• Serial Interface for Extended Control
• Fine Adjustment of Input Full-Scale Range and Offset
• Duty Cycle Corrected Sample Clock
Key Specifications
• Resolution 8 Bits
• Max Conversion Rate 500 MSPS (min)
• Bit Error Rate 10-18 (typ)
• ENOB @ 250 MHz Input 7.5 Bits (typ)
• DNL ±0.15 LSB (typ)
• Power Consumption
• Operating 1.4 W (typ)
• Power Down Mode 3.5 mW (typ)