ADC07D1520NOPB中文资料德州仪器数据手册PDF规格书

General Description

The ADC07D1520 is a dual, low power, high performance

CMOS analog-to-digital converter. The ADC07D1520 digitizes

signals to 7 bits of resolution at sample rates up to 1.5

GSPS. Its features include a test pattern output for system

debug, a clock phase adjust, and selectable output demultiplexer

modes. This device is guaranteed to have no missing

codes over the full operating temperature range. The unique

folding and interpolating architecture, the fully differential

comparator design, the innovative design of the internal sample-

and-hold amplifier and the self-calibration scheme enable

a very flat response of all dynamic parameters beyond

Nyquist, producing a high 6.8 Effective Number of Bits

(ENOB) with a 748 MHz input signal and a 1.5 GHz sample

rate while providing a 10-18 Code Error Rate (C.E.R.) Output

formatting is offset binary and the Low Voltage Differential

Signaling (LVDS) digital outputs are compatible with IEEE

1596.3-1996, with the exception of an adjustable common

mode voltage between 0.8V and 1.2V.

Each converter has a selectable output demultiplexer which

feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected,

the output data rate is reduced to half the input sample

rate on each bus. When Non-Demultiplexed Mode is selected,

the output data rate on channels DI and DQ is at the same

rate as the input sample clock. The two converters can be

interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 3.5 mW in the

Power Down Mode and is available in a leaded or lead-free,

128-pin, thermally enhanced, exposed pad LQFP and operates

over the Industrial (-40°C ≤ TA ≤ +85°C) temperature

range.

特性 Features

● Single +1.9V ±0.1V Operation

● Interleave Mode for 2x Sample Rate

● Multiple ADC Synchronization Capability

● Adjustment of Input Full-Scale Range, Clock Phase, and

Offset

● Choice of SDR or DDR Output Clocking

● 1:1 or 1:2 Selectable Output Demux

● Second DCLK Output

● Duty Cycle Corrected Sample Clock

● Test pattern

Key Specifications

● Resolution 7 Bits

● Max Conversion Rate 1.5 GSPS (max)

● Code Error Rate 10-18 (typ)

● ENOB @ 748 MHz Input 6.8 Bits (typ)

● DNL ±0.15 LSB (typ)

● Power Consumption (Non-DES Mode)

— Operating in 1:2 Demux Mode 1.9 W (typ)

— Power Down Mode 2.5 mW (typ)

Applications

● Direct RF Down Conversion

● Digital Oscilloscopes

● Satellite Set-top boxes

● Communications Systems

● Test Instrumentation