PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs

GENERAL DESCRIPTION The AD9573 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for PCI-e applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency syn

文件：297.53 Kbytes 页数：12 Pages

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PCI-Express时钟发生器IC，PLL内核，分频器，两路输出

AD9573是一款高度集成的双路输出时钟发生器 ， 包括一个针对PCI-e应用而优化的片内PLL内核 。 整数N分频PLL设计基于ADI公司成熟的高性能、低抖动频率合成器系列 ， 可实现线路卡的较高性能 。 这款器件也适合相位噪声和抖动要求严格的其它应用。 PLL部分由低噪声鉴频鉴相器(PFD)、精密电荷泵、低相位噪声压控振荡器(VCO)、预编程的反馈分频器和输出分频器组成。\n\n 通过连接一个外部25 MHz晶振，可以将100 MHz和33.33 MHz输出频率锁定至输入参考。输出分频比和反馈分频比可针对所要求的输出速率进行预编程。无需外部环路滤波器，从而节省宝贵的设计 • 完全集成的VCO/PLL内核\n均方根抖动：0.54 ps（12 kHz至20 MHz）\n输入晶振频率：25 MHz\n\n• 针对100 MHz、33.33 MHz提供预设分频比\n\n• LVDS/LVCMOS 输出格式\n\n\n\n• 集成环路滤波器\n\n• 4.4 mm × 5.0 mm TSSOP封装，节省空间\n\n• 功耗：0.235 W\n\n• 3.3 V 工作电压;

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PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs

GENERAL DESCRIPTION The AD9573 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for PCI-e applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency syn

文件：297.53 Kbytes 页数：12 Pages

AD

亚德诺

PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs

GENERAL DESCRIPTION The AD9573 provides a highly integrated, dual output clock generator function including an on-chip PLL core that is optimized for PCI-e applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency syn

文件：297.53 Kbytes 页数：12 Pages

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Package：16-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PCI CLCOK GEN 25MHZ 16TSSOP

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Package：16-TSSOP（0.173"，4.40mm 宽）；包装：卷带（TR）剪切带（CT）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 应用特定时钟/定时 描述：IC PCI CLCOK GEN 25MHZ 16TSSOP

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