AD9549BCPZ中文资料亚德诺数据手册PDF规格书

GENERAL DESCRIPTION

The AD9549 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9549 generates an output clock, synchronized to one of two external input references. The external references may contain significant time jitter, also specified as phase noise. Using a digitally controlled loop and holdover circuitry, the AD9549 continues to generate a clean (low jitter), valid output clock during a loss of reference condition, even when both references have failed.

The AD9549 operates over an industrial temperature range of −40°C to +85°C.

FEATURES

Flexible reference inputs

Input frequencies: 8 kHz to 750 MHz

Two reference inputs

Loss of reference indicators

Auto and manual holdover modes

Auto and manual switchover modes

Smooth A-to-B phase transition on outputs

Excellent stability in holdover mode

Programmable 16 + 1-bit input divider, R

Differential HSTL clock output

Output frequencies to 750 MHz

Low jitter clock doubler for frequencies of >400 MHz

Single-ended CMOS output for frequencies of <150 MHz

Programmable digital loop filter (<1 Hz to ~100 kHz)

High speed digitally controlled oscillator (DCO) core

Direct digital synthesizer (DDS) with integrated 14-bit DAC

Excellent dynamic performance

Programmable 16 + 1-bit feedback divider, S

Software controlled power-down

Available 64-lead LFCSP package

APPLICATIONS

Network synchronization

Reference clock jitter cleanup

SONET/SDH clocks up to OC-192, including FEC

Stratum 3/3E reference clocks

Wireless base station, controllers

Cable infrastructure

Data communications