AD9171BBPZRL中文资料亚德诺数据手册PDF规格书

FEATURES

► Supports single-band wireless applications

► 1 complex data input channel per RF DAC

► 516 MSPS maximum complex input data rate per input channel

► 1 independent NCO per input channel

► Proprietary, low spurious and distortion design

► 2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output

► SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output

► Flexible 8-lane, 15.4 Gbps JESD204B interface

► Supports single-band use cases

► Supports 12-bit high density mode for increased data throughput

► Multiple chip synchronization

► Supports JESD204B Subclass 1

► Selectable interpolation filter for a complete set of input data

rates

► 2×, 3×, 4×, and 6× configurable data channel interpolation

► 6× and 8× configurable final interpolation

► Final 48-bit NCO that operates at the DAC rate to support

frequency synthesis up to 3.1 GHz

► Transmit enable function allows extra power saving and downstream

circuitry protection

► High performance, low noise PLL clock multiplier

► Supports 6.2 GSPS DAC update rate

► Observation ADC clock driver with selectable divide ratios

► Low power

► 1.45 W at 6 GSPS, single-channel mode

► 10 mm × 10 mm, 144-ball BGA_ED with metal enhanced thermal

lid, 0.80 mm pitch

APPLICATIONS

► Wireless communications infrastructure

► Single-band base station radios

► Instrumentation, automatic test equipment (ATE)