AD9081BBPZ-4D4AC中文资料亚德诺数据手册PDF规格书

FEATURES

► Flexible, reconfigurable common platform design

► 4 DACs and 4 ADCs (4D4A)

► Supports single, dual, and quad band

► Datapaths and DSP blocks are fully bypassable

► DAC to ADC sample rate ratios of 1, 2, 3, and 4

► On-chip PLL with multichip synchronization

► External RFCLK input option for off-chip PLL

► Maximum DAC sample rate up to 12 GSPS

► Maximum data rate up to 12 GSPS using JESD204C

► Useable analog bandwidth to 8 GHz

► Maximum ADC sample rate up to 4 GSPS

► Maximum data rate up to 4 GSPS using JESD204C

► 7.5 GHz analog input full power bandwidth (−3 dB)

► ADC ac performance at 4 GSPS, input at −2.7 GHz, −1 dBFS

► Full-scale input voltage: 1.4 V p-p

► Noise density: −147.5 dBFS/Hz

► Noise figure: 26.8 dB

► HD2: −67 dBFS

► HD3: −73 dBFS

► Worst other (excluding HD2 and HD3): −79 dBFS at 2.7 GHz

► DAC ac performance at 12 GSPS

► Full-scale output current range: 6.43 mA to 37.75 mA

► Two-tone IMD3 (−7 dBFS per tone): −78.9 dBc

► NSD, single-tone at 3.7 GHz: −155.1 dBc/Hz

► SFDR, single-tone at 3.7 GHz: −70 dBc

► Versatile digital features

► Configurable or bypassable DDCs and DUCs

► 8 fine complex DUCs and 4 coarse complex DUCs

► 8 fine complex DDCs and 4 coarse complex DDCs

► 48-bit NCO per DUC or DDC

► Programmable 192-tap PFIR filter for receive equalization

► Supports 4 different profile settings loaded via GPIO

► Programmable delay per datapath

► Receive AGC support

► Fast detect with low latency for fast AGC control

► Signal monitor for slow AGC control

► Transmit DPD support

► Fine DUC channel gain control and delay adjust

► Coarse DDC delay adjust for DPD observation path

► Auxiliary features

► Fast frequency hopping and direct digital synthesis (DDS)

► Low latency loopback mode (receive datapath data can be

routed to the transmit datapaths)

► ADC clock driver with selectable divide ratios

► Power amplifier downstream protection circuitry

► On-chip temperature monitoring unit

► Flexible GPIO pins

► TDD power savings option and sharing ADCs

► SERDES JESD204B/JESD204C interface, 16 lanes up to

24.75 Gbps

► 8 lanes JESD204B/C transmitter (JTx) and 8 lanes

JESD204B/C receiver (JRx)

► JESD204B compliance with the maximum 15.5 Gbps

► JESD204C compliance with the maximum 24.75 Gbps

► Supports real or complex digital data (8-, 12-, 16-, or 24-bit)

► 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

APPLICATIONS

► Wireless communications infrastructure

► Microwave point to point, E-band, and 5G mmWave

► Broadband communications systems

► DOCSIS 3.1 and 4.0 CMTS

► Phased array radar and electronic warfare

► Electronic test and measurement systems