AD835AR集成电路（IC）的模拟乘法器、除法器规格书PDF中文资料

AD835AR属于集成电路（IC）的模拟乘法器、除法器。由亚德诺半导体技术有限公司制造生产的AD835AR模拟乘法器、除法器模拟乘法器获取两个或更多模拟信号，并产生这些信号的乘积或乘积之和的输出。此类电路可用于实现相关计算功能，例如计算平方（对两个输入都施加相同的信号）和平方根。应用可能包括可变增益放大器、环形调制器、乘积检测器、混频器、增益控制、真 RMS 转换器和脉冲幅度调制器 (PAM)。

GENERAL DESCRIPTION

The AD835 is a complete four-quadrant, voltage output analog multiplier, fabricated on an advanced dielectrically isolated complementary bipolar process. It generates the linear product of its X and Y voltage inputs with a −3 dB output bandwidth of 250 MHz (a small signal rise time of 1 ns). Full-scale (−1 V to +1 V) rise to fall times are 2.5 ns (with a standard RL of 150 Ω), and the settling time to 0.1 under the same conditions is typically 20 ns.

Its differential multiplication inputs (X, Y) and its summing input (Z) are at high impedance. The low impedance output voltage (W) can provide up to ±2.5 V and drive loads as low as 25 Ω. Normal operation is from ±5 V supplies.

Though providing state-of-the-art speed, the AD835 is simple to use and versatile. For example, as well as permitting the addition of a signal at the output, the Z input provides the means to operate the AD835 with voltage gains up to about ×10. In this capacity, the very low product noise of this multiplier (50 nV/√Hz) makes it much more useful than earlier products.

The AD835 is available in an 8-lead PDIP package (N) and an 8-lead SOIC package (R) and is specified to operate over the −40°C to +85°C industrial temperature range.

FEATURES

Simple: basic function is W = XY + Z

Complete: minimal external components required

Very fast: Settles to 0.1 of full scale (FS) in 20 ns

DC-coupled voltage output simplifies use

High differential input impedance X, Y, and Z inputs

Low multiplier noise: 50 nV/√Hz

APPLICATIONS

Very fast multiplication, division, squaring

Wideband modulation and demodulation

Phase detection and measurement

Sinusoidal frequency doubling

Video gain control and keying

Voltage-controlled amplifiers and filters