AD802中文资料155 Mbps Clock and Data Recovery IC数据手册ADI规格书

描述 Description

The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data re timing on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively. 155 Mbps STS-3 or STM-1 are supported by the AD802-155.Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The phase-lock loop than acquires the phase of the input data, and ensures the phase of the output signals track changes in the phase of the output data. The loop damping of the circuit is dependent of the value of a user selected capacitor; this defines jitter peaking and performance and impacts acquisition time. The devices exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within 4 X 105 bit periods when using a damping factor of 5.During the process of acquisition the frequency detector provides a Frequency Acquisition (FRAC) signal which indicates that the device has not yet locked onto the input data. This signal is a series of pulses which occur at the points of cycle slip between the input data and the synthesized clock signal. Once the circuit has acquired frequency lock no pulses occur at the FRAC output.The inclusion of a precisely trimmed VCO in the device eliminates the need for external components for setting center frequency, and the need for trimming of those components.The VCO provides a clock output within ±20% of the device center frequency in the absence of input data.The AD800 and AD802 exhibit virtually no pattern jitter, due to the performance of the patented phase detector.Total loop jitter is 20° peak-to-peak.Jitter bandwidth is dictated by mask programmable fractional loop bandwidth.The AD800, used for data rates All of the devices operate with a single +5 Vor -5.2 V supply.

简介

AD802属于开发板套件编程器的评估板-运算放大器。由制造生产的AD802评估板 - 运算放大器运算放大器评估板是装有元器件的电路，用于提供特定集成电路或器件的工作实例。该产品族中的电路板提供了运算放大器实例。每个 IC 的通道类型有单通道、双通道、三通道、四通道和八通道，放大器类型包括音频、自动归零、缓冲器、斩波器、电流反馈、电流检测、差动、差分、四通道、仪表、隔离、J-FET、限幅、对数、功率、可编程增益、采样保持、跨阻、可变增益、视频、电压反馈和零漂移。