AD802-155BR中文资料亚德诺数据手册PDF规格书

PRODUCT DESCRIPTION

The AD800 and AD802 employ a second order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero, NRZ, data. This architecture is capable of supporting data rates between 20 Mbps and 160 Mbps. The products described here have been defined to work with standard telecommunications bit rates. 45 Mbps DS-3 and 52 Mbps STS-1 are supported by the AD800-45 and AD800-52 respectively. 155 Mbps STS-3 or STM-1 are supported by the AD802-155.

Unlike other PLL-based clock recovery circuits, these devices do not require a preamble or an external VCXO to lock onto input data. The circuit acquires frequency and phase lock using two control loops. The frequency acquisition control loop initially acquires the clock frequency of the input data. The phase-lock loop then acquires the phase of the input data, and ensures that the phase of the output signals track changes in the phase of the input data. The loop damping of the circuit is dependent on the value of a user selected capacitor; this defines jitter peaking performance and impacts acquisition time. The devices exhibit 0.08 dB jitter peaking, and acquire lock on random or scrambled data within 4 × 105 bit periods when using a damping factor of 5.

FEATURES

Standard Products

44.736 Mbps—DS-3

51.84 Mbps—STS-1

155.52 Mbps—STS-3 or STM-1

Accepts NRZ Data, No Preamble Required

Recovered Clock and Retimed Data Outputs

Phase-Locked Loop Type Clock Recovery—No Crystal Required

Random Jitter: 208 Peak-to-Peak

Pattern Jitter: Virtually Eliminated

10KH ECL Compatible

Single Supply Operation: –5.2 V or +5 V

Wide Operating Temperature Range: –408C to +858C