AD7451BRM

Pseudo Differential, 1MSPS, 12- & 10-Bit ADCs in 8-lead SOT-23

GENERALDESCRIPTION TheAD7441/AD74511are,respectively,10-/12-bithighspeed,lowpower,single-supply,successiveapproximation(SAR),analog-to-digitalconverters(ADCs)thatfeatureapseudodifferentialanaloginput.Thesepartsoperatefromasingle2.7Vto5.25Vpowersupplyandachiev

AD7451BRMZ

Pseudo Differential Input, 1 MSPS, 10-/12-Bit ADCs in an 8-Lead SOT-23

GENERALDESCRIPTION TheAD7441/AD74511are,respectively,10-/12-bithighspeed,lowpower,single-supply,successiveapproximation(SAR),analog-to-digitalconverters(ADCs)thatfeatureapseudodifferentialanaloginput.Thesepartsoperatefromasingle2.7Vto5.25Vpowersupplyandachiev

AD7451BRMZ

Package：8-TSSOP，8-MSOP（0.118"，3.00mm 宽）；包装：管件 类别：集成电路（IC） 模数转换器（ADC） 描述：IC ADC 12BIT SAR 8MSOP

AD7451BRT

PseudoDifferential,1MSPS,12-&10-BitADCsin8-leadSOT-23

GENERALDESCRIPTION TheAD7441/AD74511are,respectively,10-/12-bithighspeed,lowpower,single-supply,successiveapproximation(SAR),analog-to-digitalconverters(ADCs)thatfeatureapseudodifferentialanaloginput.Thesepartsoperatefromasingle2.7Vto5.25Vpowersupplyandachiev

AK7451

zerolatencyanglesensoric

AM7451P

P-Channel50-V(D-S)MOSFET

ANX7451

106ActiveMux(6x4)withIntegratedRe-timersforUSB3.2/DisplayPort1.4

Features *Built-inre-timers —Integratedre-timersforUSB3.2uptoGen2@10Gbps —SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) —Integratedre-timers(Linktraining-tunablePHYrepeater)forD

ANX7451

20GActiveMux(2x2)withIntegratedRe-timerandCCDetectionforUSB3.2

Features Built-inre-timer −Integratedre-timerforUSB3.2uptoGen2@2x10Gbpsforacombined20Gdatathroughput −SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) −Supportsbothhost(source

ANX7451

10GActiveMux(1x2)withIntegratedRe-timerandCCDetectionforUSB3.2

Features Built-inre-timer −Integratedre-timerforUSB3.2uptoGen2@10Gbps −SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification(Appendix-E) −Losscompensationtorecoverupto23dBchannelloss Integrat

ANX7451

20GActiveRetimerforUSB3.2

Features Built-inre-timer -Integratedre-timerforUSB3.2withtwolanesuptoGen2@10Gbpseachforacombined20Gthroughput -SupportsbothSeparateReferenceClockIndependentSSC(SRIS)andBit-LevelRe-timer(BLR)ArchitecturesofUSB3.2Specification -Supportsbothhost(source)