24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC Settling and True Rail-to-Rail Buffers

文件：1.11819 Mbytes 页数：63 Pages

AD

亚德诺

Zero Drift, High Voltage, Low Power, Programmable Gain Instrumentation Amplifier

文件：1.05142 Mbytes 页数：59 Pages

AD

亚德诺

24位、250 KSPS Σ-Δ型ADC，具有20 MS建立时间和真轨到轨缓冲器

AD7175-2是一款低噪声、快速建立、多路复用、2/4通道（全差分/伪差分）Σ-Δ型模数转换器(ADC)，适合低带宽输入。针对完全建立的数据，该器件最大通道扫描速率为50 kSPS (20 µs)。该器件的输出数据速率范围为5 SPS至250 kSPS。\n\n AD7175-2集成关键的模拟和数字信号调理模块，可让用户针对使用的每个模拟输入通道单独进行配置。用户可为各通道单独选择功能。模拟输入端和外部基准电压输入端的集成真轨到轨缓冲器可提供易于驱动的高阻抗输入。精密2.5 V低漂移(2 ppm/癈)带隙内部基准电压源（带输出基准电压源缓冲器）增加了嵌入式功能，同时减少了外部元件数 • 快速且灵活的输出速率：5 SPS至250 kSPS\n\n• 通道扫描速率：50 kSPS/通道（20 μs建立时间）\n\n• 性能规格\n• 17.2位无噪声分辨率(250 kSPS)\n\n• 20位无噪声分辨率(2.5 kSPS)\n\n• 24位无噪声分辨率(20 SPS)\n\n• 积分非线性(INL)：FSR的±1 ppm\n\n\n\n\n• 50 Hz和60 Hz抑制：85 dB，建立时间为50 ms\n\n• 用户可配置的输入通道\n• 2个全差分通道或4个单端通道\n\n• 交叉点多路复用器\n\n\n\n\n• 2.5 V片内基准电压源（±2 ppm/°C漂移）\n;

ADI

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC with 20 us Settling and True Rail-to-Rail Buffers

GENERAL DESCRIPTION The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SP

文件：1.20509 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC Settling and True Rail-to-Rail Buffers

文件：1.11819 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC Settling and True Rail-to-Rail Buffers

文件：1.11819 Mbytes 页数：63 Pages

AD

亚德诺

24-Bit, 250 kSPS, Sigma-Delta ADC Settling and True Rail-to-Rail Buffers

文件：1.11819 Mbytes 页数：63 Pages

AD

亚德诺