GENERAL DESCRIPTION

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.

FEATURES

SNR = 65.8 dBFS at fIN up to 250 MHz at 500 MSPS

ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)

SFDR = 80 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)

Excellent linearity

DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical

Integrated 16k × 12 FIFO

FIFO readback options

12-bit parallel CMOS at 62.5 MHz

6-bit DDR LVDS interface

SPORT at 62.5 MHz

SPI at 25 MHz

High speed synchronization capability

1 GHz full power analog bandwidth

Integrated input buffer

On-chip reference, no external decoupling required

Low power dissipation

695 mW at 500 MSPS

Programmable input voltage range

1.18 V to 1.6 V, 1.5 V nominal

1.9 V analog and digital supply operation

1.9 V or 3.3 V SPI and SPORT operation

Clock duty cycle stabilizer

Integrated data clock output with programmable clock and

data alignment

APPLICATIONS

Wireless and wired broadband communications

Communications test equipment

Power amplifier linearization

AD6641-500EBZ属于开发板，套件，编程器 > 评估和演示板及套件。亚德诺半导体技术有限公司制造生产的AD6641-500EBZ评估和演示板及套件该系列产品提供了一种方便的方法，在经过验证的实施环境中评估某些重点器件的性能或特性。评估方法通常有完善的文档说明，并且视乎具体情况由评估软件提供支持。产品通常由印刷电路板组成，板上已装有重点器件以及必要或有用的支持元器件，另外也可能包括其他组件，例如电缆或电源。对于数量特别多或类别独特的器件类别(如 ADC、DAC 和开关模式电源)，评估平台可组合为一个单独的产品系列。