AD6624A中文资料亚德诺数据手册PDF规格书

PRODUCT DESCRIPTION

The AD6624A is a four-channel (quad) digital receive signal processor (RSP) with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable-coefficient decimating filter.

FEATURES

100 MSPS Wideband Inputs (14 Linear Bits Plus 3 RSSI)

Dual High-Speed Data Input Ports

Four Independent Digital Receivers in Single Package

Digital Resampling for Noninteger Decimation Rates

Programmable Decimating FIR Filters

Programmable Attenuator Control for Clip Prevention and External Gain Ranging via Level Indicator

Flexible Control for Multicarrier and Phased Array

3.3 V I/O, 2.5 V CMOS Core

User-Configurable Built-In Self-Test (BIST) Capability

JTAG Boundary Scan

APPLICATIONS

Multicarrier, Multimode Digital Receivers GSM, IS136, EDGE, PHS, IS95

Micro and Pico Cell Systems

Wireless Local Loop

Smart Antenna Systems

Software Radios

In-Building Wireless Telephony