AD6472中文资料亚德诺数据手册PDF规格书

GENERAL DESCRIPTION

The AD6472 is a single chip analog front end for two pair or single pair HDSL applications that use 1168 Kbps or 2.32 Mbps data rates.

The AD6472 integrates all the transmit and receive functional blocks together with the timing recovery DAC. The digital interface is designed to support industry standard digital transceivers.

FEATURES

Integrated Front End for Single Pair or Two Pair HDSL Systems

Meets ETSI Specifications

Supports 1168 Kbps and 2.32 Mbps

Transmit and Receive Signal Path Functions

Receive Hybrid Amplifier, PGA and ADC

Transmit DAC, Filter and Differential Outputs

Programmable Filters

Control and Ancillary Functions

Timing Recovery DAC

Normal Loopback and Low Power Modes

Simple Interface-to-Digital Transceivers

Single 5 V Power Supply

Power Consumption: 320 mW—(Excluding Driver)

Package: 80-Lead MQFP

Operating Temperature: –40℃ to +85℃