AD633J集成电路（IC）的模拟乘法器、除法器规格书PDF中文资料

AD633J属于集成电路（IC）的模拟乘法器、除法器。由亚德诺半导体技术有限公司制造生产的AD633J模拟乘法器、除法器模拟乘法器获取两个或更多模拟信号，并产生这些信号的乘积或乘积之和的输出。此类电路可用于实现相关计算功能，例如计算平方（对两个输入都施加相同的信号）和平方根。应用可能包括可变增益放大器、环形调制器、乘积检测器、混频器、增益控制、真 RMS 转换器和脉冲幅度调制器 (PAM)。

GENERAL DESCRIPTION

The AD633 is a functionally complete, four-quadrant, analog multiplier. It includes high impedance, differential X and Y inputs, and a high impedance summing input (Z). The low impedance output voltage is a nominal 10 V full scale provided by a buried Zener. The AD633 is the first product to offer these features in modestly priced 8-lead PDIP and SOIC packages.

FEATURES

4-quadrant multiplication

Low cost, 8-lead SOIC and PDIP packages

Complete—no external components required

Laser-trimmed accuracy and stability

Total error within 2 of full scale

Differential high impedance X and Y inputs

High impedance unity-gain summing input

Laser-trimmed 10 V scaling reference

APPLICATIONS

Multiplication, division, squaring

Modulation/demodulation, phase detection

Voltage-controlled amplifiers/attenuators/filters