AD4630-16BBCZ-RL集成电路（IC）的模数转换器（ADC）规格书PDF中文资料

AD4630-16BBCZ-RL属于集成电路（IC）的模数转换器（ADC）。由亚德诺半导体技术有限公司制造生产的AD4630-16BBCZ-RL模数转换器（ADC）模数转换器（ADC、A/D 或 A 转 D）对模拟信号进行采样，例如由麦克风采集的声音或传感器的输出，然后将其转换为数字信号。一般来说，数字输出是二进制补码二进制数，与输入成比例。输入类型可能是差分、伪差分或单端输入。模数转换器可按照位数、采样率、输入数、接口、转换器数和架构（例如自适应增量、双斜率、折叠、流水线、SAR、三角积分、两步式）进行选择。

GENERAL DESCRIPTION

The AD4630-16/AD4632-16 are 2-channel, simultaneous sampling,

Easy Drive™, 2 MSPS or 500 kSPS successive approximation register

(SAR), analog-to-digital converters (ADCs). With a guaranteed

maximum ±3 ppm integral nonlinearity (INL) and no missing codes

at 16-bits, the AD4630-16/AD4632-16 achieve excellent precision

from −40°C to +125°C. Figure 1 shows the functional architecture of

the AD4630-16/AD4632-16.

A low-drift, internal precision-reference buffer eases voltage-reference

sharing with other system circuitry. The AD4630-16/

AD4632-16 offer a typical dynamic range of 97.4 dB when using a 5

V reference. The low noise floor enables signal chains utilizing less

gain and lower power. A block averaging filter with programmable

decimation ratio is available and can reduce noise for low-bandwidth

signals, improving accuracy. The wide differential input and

common-mode ranges allow inputs to use the full voltage reference

(±VREF) range without saturating, simplifying signal-conditioning

requirements and system calibration. The improved settling of the

Easy Drive analog inputs broadens the selection of analog front end

(AFE) components compatible with the AD4630-16/AD4632-16.

Both single-ended and differential signals are supported.

The versatile Flexi-SPI serial-peripheral interface (SPI) eases host

processor and ADC integration. A wide data-clocking window, multiple

serial-data output (SDO) lanes, and optional dual data rate

(DDR) data clocking can reduce the serial clock to 10 MHz while

operating at a sample rate of 2 MSPS. Echo clock mode can relax

the timing requirements and simplify the use of digital isolators.

The ball grid array (BGA) package of the AD4630-16/AD4632-16

integrates all critical power supply and reference bypass capacitors,

reducing the footprint and system-component count, and lessening

sensitivity to board layout.

FEATURES

► High performance

► Throughput: 2 MSPS (AD4630-16) or 500 kSPS (AD4632-16)

per channel maximum

► INL: ±3 ppm maximum from −40°C to +125°C

► SNR: 97.4 dB typical

► THD: −127 dB typical

► NSD: −157.4 dBFS/Hz typical

► Low power

► 15 mW per channel at 2 MSPS

► 5 mW per channel at 500 kSPS

► 1.5 mW per channel at 10 kSPS

► Easy Drive features reduce system complexity

► Low 0.6 μA input current for DC inputs

► Wide common-mode input range: −(1/128) × VREF to

+(129/128) × VREF

► Flexible external reference voltage range: 4.096 V to 5 V

► Accurate integrated reference buffer with 2 μF bypass capacitor

► Programmable block averaging filter with up to 216 decimation

► Extended sample resolution to 30 bits

► Overrange and synchronization bits

► Flexi-SPI digital interface

► 1, 2, or 4 SDO lanes per channel allows slower SCK

► Echo clock mode simplifies use of digital isolator

► Compatible with 1.2 V to 1.8 V logic

► 7 mm × 7 mm 64-Ball CSP_BGA package with internal supply

and reference capacitors to help reduce system footprint

APPLICATIONS

► Automatic test equipment

► Digital control loops

► Medical instrumentation

► Seismology

► Semiconductor manufacturing

► Scientific instrumentation