AD1893JST集成电路（IC）的音频专用规格书PDF中文资料

AD1893JST属于集成电路（IC）的音频专用。由亚德诺半导体技术有限公司制造生产的AD1893JST音频专用音频专用的半导体器件专为音频信号的滤波、驱动、放大、转换和接口而设计。特征包括功能、应用、通道数、接口、电压和规格。应用包括音频系统、汽车音频、消费类音频、乐器、专业音频、通信系统、电信系统、数字音频、驱动器、前置放大器、信号混合、信号处理、语音触发器解决方案和 10 Base-T。

PRODUCT OVERVIEW

The AD1893 SamplePort is a fully digital, stereo Asynchronous Sample Rate Converter (ASRC) that solves sample rate interfacing and compatibility problems in digital audio equipment. Conceptually, this converter interpolates the input data up to a very high internal sample rate with a time resolution of 300 ps, then decimates down to the desired output sample rate. The AD1893 is intended for 16-bit low cost, non-varispeed applications where low voltage, low power (i.e., battery-powered) operation is required. Refer to the AD1890/AD1891 data sheet for other products in the SamplePort family. This device is asynchronous because the frequency and phase relationships between the input and output sample clocks (both are inputs to the AD1893 ASRC) are arbitrary and need not be related by a simple integer ratio. There is no need to explicitly select or program the input and output sample clock frequencies, as the AD1893 automatically senses the relationship between the two clocks. The input and output sample clock frequencies can nominally range from 8 kHz to 56 kHz, and the ratio between them can vary from approximately 1:2 to 2:1.

The AD1893 uses multirate digital signal processing techniques to construct an output sample stream from the input sample stream. The input word width is 4 to 16 bits for the AD1893. Shorter input words are automatically zero-filled in the LSBs. The output word width is 24 bits. The user can receive as many of the output bits as desired. Internal arithmetic is performed with 22-bit coefficients and 27-bit accumulation. The digital samples are processed with unity gain.

FEATURES

Low Cost

LQFP and PDIP Packages

3 V Supply Performance Specified—Very Low Power

Automatically Senses Sample Frequencies—No Programming Required

Rejects Sample Clock Jitter

Accommodates Dynamically Changing Asynchronous Sample Clocks

8 kHz to 56 kHz Sample Clock Frequency Range

Approximately 1:2 to 2:1 Ratio Between Sample Clocks

–96 dB THD+N at 1 kHz

96 dB Dynamic Range

Optimal Clock Tracking Control—Slow/Fast Settling Modes

Linear Phase in All Modes

Automatic Output Mute

Flexible Four-Wire Serial Interfaces with Right-Justified

Mode

Power-Down Mode

On-Chip Oscillator

APPLICATIONS

Consumer CD-R, DAT, DCC, MD and 8 mm Video Tape

Recorders Including Portables

Digital Audio Communication/Network Systems

Computer Multimedia Systems