Radiation Hardened EDAC (Error Detection and Correction)

Description The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory re

文件：489.68 Kbytes 页数：4 Pages

INTERSIL

Radiation Hardened EDAC (Error Detection and Correction)

Features • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96721 and Intersil’s QM Plan • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose >300K RAD (Si) • Single Event Upset (SEU) Immunity:

文件：683.51 Kbytes 页数：4 Pages

RENESAS

瑞萨

Radiation Hardened EDAC (Error Detection and Correction)

Renesas

瑞萨

Radiation Hardened EDAC (Error Detection and Correction)

Description The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory re

文件：489.68 Kbytes 页数：4 Pages

INTERSIL

Radiation Hardened EDAC (Error Detection and Correction)

Features • Devices QML Qualified in Accordance with MIL-PRF-38535 • Detailed Electrical and Screening Requirements are Contained in SMD# 5962-96721 and Intersil’s QM Plan • 1.25 Micron Radiation Hardened SOS CMOS • Total Dose >300K RAD (Si) • Single Event Upset (SEU) Immunity:

文件：683.51 Kbytes 页数：4 Pages

RENESAS

瑞萨

Radiation Hardened EDAC (Error Detection and Correction)

Description The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error detection and correction circuit. It uses a modified Hamming code to generate a 6-bit check word from each 16-bit data word. The check word is stored with the data word during a memory write cycle; during a memory re

文件：489.68 Kbytes 页数：4 Pages

INTERSIL