丝印：ACT16823；Package：SSOP；18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Flow-Through Architecture Optimizes PCB Layout Distributed VCC

文件：283.96 Kbytes 页数：11 Pages

TI

德州仪器

丝印：ACT16823；Package：SSOP；18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Flow-Through Architecture Optimizes PCB Layout Distributed VCC

文件：283.96 Kbytes 页数：11 Pages

TI

德州仪器

丝印：ACT16823；Package：SSOP；18-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS

EPICE (Enhanced-Performance Implanted CMOS) 1-mm Process Members of the Texas Instruments WidebusE Family Inputs Are TTL-Voltage Compatible Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity Flow-Through Architecture Optimizes PCB Layout Distributed VCC

文件：283.96 Kbytes 页数：11 Pages

TI

德州仪器

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：99.78 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus-interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：99.78 Kbytes 页数：12 Pages

PHI

PHI

18-bit bus interface D-type flip-flop with reset and enable 3-State

DESCRIPTION The 74ABT16823A 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. FEATURES • Two sets of high speed parallel registers with positive edge

文件：86.11 Kbytes 页数：12 Pages

PHI

PHI