A80960HD80SL2GK数据手册Intel中文资料规格书

描述 Description

Intel’s 80960Hx Processor
Intel’s 80960Hx processor provides new performance levels while maintaining backward compatibility (pin1 and software) with the i960 CA/CF processor. This newest member of the family of i960 32-bit, RISC-style, embedded processors allows customers to create scalable designs that meet multiple price and performance points. This is accomplished by providing processors that can run at the bus speed or faster using Intel’s clock multiplying technology (Table 1).The 80960Hx core is capable of issuing 150 million instructions per second, using a sophisticated instruction scheduler that allows the processor to sustain a throughput of two instructions every core clock, with a peak performance of three instructions per clock. The 80960Hx-series comprises three processors, which differ in the ratio of core clock speed to external bus speed.Product

特性 Features

■ 32-Bit Parallel Architecture
   —Load/Store Architecture
   —Sixteen 32-Bit Global Registers
   —Sixteen 32-Bit Local Registers
   —1.28 Gbyte Internal Bandwidth (80 MHz)
   —On-Chip Register Cache
■ Processor Core Clock
   —80960HA is 1x Bus Clock
   —80960HD is 2x Bus Clock
   —80960HT is 3x Bus Clock
■ Binary Compatible with Other 80960 Processors
■ Issue Up To 150 Million Instructions per Second
■ High-Performance On-Chip Storage
   —16 Kbyte Four-Way Set-Associative Instruction Cache
   —8 Kbyte Four-Way Set-Associative Data Cache
   —2 Kbyte General Purpose RAM
   —Separate 128-Bit Internal Paths For Instructions/Data
■ 3.3 V Supply Voltage
   —5 V Tolerant Inputs
   —TTL Compatible Outputs
■ Guarded Memory Unit
   —Provides Memory Protection
   —User/Supervisor Read/Write/Execute
■ 32-Bit Demultiplexed Burst Bus
   —Per-Byte Parity Generation/Checking
   —Address Pipelining Option
   —Fully Programmable Wait State Generator
   —Supports 8-, 16- or 32-Bit Bus Widths
   —160 Mbyte/s External Bandwidth (40 MHz)
■ High-Speed Interrupt Controller
   —Up to 240 External Interrupts
   —31 Fully Programmable Priorities
   —Separate, Non-maskable Interrupt Pin
■ Dual On-Chip 32-Bit Timers
   —Auto Reload Capability and One-Shot
   —CLKIN Prescaling, ÷1, 2, 4 or 8
   —JTAG Support - IEEE 1149.1 Compliant