A20中文资料麦瑞半导体数据手册PDF规格书

General Description

The SM803020 is a dual-PLL clock generator that achieves ultra-low, 74.2fs_rms output jitter at 156.25MHz output frequency. It accepts a crystal input or a reference input.

Each output channel is individually configurable to a differential PECL, LVDS, HCSL, or CMOS output logic level. PECL is selected by default, but can be overridden through SPI. It is packaged in a dual-row 84-pin 7mm x 7mm package.

Features

• Generates twelve 156.25MHz outputs

• Independently programmable output logic:

− Output logic: LVPECL (default), LVDS, HCSL,

LVCMOS

• 74.2fs jitter at 156.25MHz (1.875MHz to 20MHz)

• Selectable inputs require 39.0625MHz input frequency

− XTAL (default)

− Differential or single-ended reference clock (SPI

selectable)

• 2.5V or 3.3V operating power supply

• Separate output power supplies:

− Different banks can be at different levels

• Industrial temperature range (–40°C to +85°C)

• Green, RoHS, and PFOS compliant

• Available in 84-pin 7mm × 7mm QFN package

Applications

• 1/10/40/100 Gigabit Ethernet