9ZXL1550BKLFT集成电路（IC）的应用特定时钟/定时规格书PDF中文资料

Features/Benefits

• LP-HCSL outputs; up to 90 IO power reduction, better

signal integrity over long traces

• Direct connect to 85Ω transmission lines; eliminates 60

termination resistors, saves 103mm2 area

• Pin compatible to the 9ZXL1530; easy upgrade to reduced

board space

• 64-VFQFPN package; smallest 15 output Z-buffer

• Fixed feedback path: ~ 0ps input-to-output delay

• 9 Selectable SMBus addresses; multiple devices can share

same SMBus segment

• Separate VDDIO for outputs; allows maximum power

savings

• PLL or bypass mode; PLL can dejitter incoming clock

• 100MHz & 133.33MHz PLL mode; legacy QPI/UPI support

• Selectable PLL BW; minimizes jitter peaking in downstream

PLL's

• Spread spectrum compatible; tracks spreading input clock

for EMI reduction

• SMBus Interface; unused outputs can be disabled

Output Features

• 15 - LP-HCSL Differential Output Pairs w/integrated

terminations (Zo = 85)