9ZML1255AKILFT中文资料瑞萨数据手册PDF规格书

特性 Features

▪ 12 Low-power HCSL (LP-HCSL) outputs

▪ Integrated terminations for 85Ω (9ZXL1255/56) and 100Ω

(9ZXL1245) systems eliminate up to 4 resistors per output pair

▪ Flexible Power Sequencing (FPS) configuration via SMBus

▪ Power Down Tolerant input (PDT); inputs: SEL_A_B#,

SADR[1:0]_tri, OE# pins

▪ Input-to-output delay: 0ps default. Programmable through 360°

▪ 2 software-configurable input-to-output delay lines

▪ Dedicated OE# pins support PCIe CLKREQ# function

▪ Up to 9 selectable SMBus addresses (9ZXL1245/55)

▪ SMBus Write Protect Pin (9ZXL1256)

▪ Selectable ZDB bandwidths minimizes jitter peaking in

cascaded ZDB topologies

▪ Hardware/SMBus control of ZDB and FOB modes

▪ Spread-spectrum compatible

▪ Up to 400MHz FOB operation

▪ 100MHz ZDB mode operation

▪ -40°C to +85°C operating temperature range

▪ 10 × 10 mm 72-VFQFPN package

Typical Applications

▪ Servers/High-performance Computing

▪ nVME Storage

▪ Networking

▪ Accelerators

▪ Industrial Control