9FGV0631CKLFT集成电路（IC）的应用特定时钟/定时规格书PDF中文资料

特性 Features

• LP-HCSL outputs; save 12 resistors compared to standard

PCIe devices

• 54mW typical power consumption; reduced thermal

concerns

• Outputs can optionally be supplied from any voltage

between 1.05V and 1.8V; maximum power savings

• OE# pins; support DIF power management

• Programmable slew rate for each output; allows tuning for

various line lengths

• Programmable output amplitude; allows tuning for various

application environments

• DIF outputs blocked until PLL is locked; clean system

start-up

• Selectable 0, -0.25 or -0.5 spread on DIF outputs;

reduces EMI

• External 25MHz crystal; supports tight ppm with 0 ppm

synthesis error

• Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

• 3.3V tolerant SMBus interface works with legacy controllers

• Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

• Space saving 5 x 5 mm 40-VFQFPN; minimal board space