Description

ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer

Specification. This buffer provides 12 output clocks for CPU Host

Bus, PCIe Gen2, or Fully Buffered DIMM applications. The outputs

are configured with two groups. Both groups (DIF 9:0) and (DIF

11:10) can be equal to or have a gear ratio to the input clock. A

differential CPU clock from a CK410B+ main clock generator,

such as the ICS932S421, drives the . The

can provide outputs up to 400MHz.

Key Specifications

• DIF output cycle-to-cycle jitter < 50ps

• DIF output-to-output skew < 100ps across all outputs in 1:1 mode

• 56-pin SSOP/TSSOP package

• RoHS compliant packaging

Features/Benefits

• Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)

• Power up default is all outputs in 1:1 mode

• DIF_(9:0) can be “gear-shifted” from the input CPU Host

Clock

• DIF_(11:10) can be “gear-shifted” from the input CPU

Host Clock

• Spread spectrum compatible

• Supports output clock frequencies up to 400 MHz

• 8 Selectable SMBus addresses

• SMBus address determines PLL or Bypass mode

9FG1200DF-1LFT属于集成电路（IC） > 应用特定时钟/定时。瑞萨科技有限公司制造生产的9FG1200DF-1LFT应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。