9FG1200-1中文资料DB1200GS Frequency Gearing Clock数据手册Renesas规格书

描述 Description

9FG1200-1 follows the Intel DB1200GS Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCIe Gen2, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock generator, such as the 932S421, drives the . The can provide outputs up to 400MHz.

特性 Features

·Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
·Power up default is all outputs in 1:1 mode
·DIF_(9:0) can be \"gear-shifted\" from the input CPU Host Clock
·DIF_(11:10) can be \"gear-shifted\" from the input CPU Host Clock
·Spread spectrum compatible
·Supports output clock frequencies up to 400 MHz
·8 Selectable SMBus addresses
·SMBus address determines PLL or Bypass mode
·DIF output cycle-to-cycle jitter < 50ps
·DIF output-to-output skew < 100ps across all outputs in 1:1 mode
·56-pin SSOP/TSSOP package
·RoHS compliant packaging