GENERAL DESCRIPTION

The 9DB202 is a high perfromance 1-to-2 Differential-to-HCSL

Jitter Attenuator designed for use in PCI Express™ systems. In

some PCI Express™ systems, such as those found in desktop PCs,

the PCI Express™ clocks are generated from a low bandwidth,

high phase noise PLL frequency synthesizer. In these systems, a

jitter-attenuating device may be necessary in order to reduce high

frequency random and deterministic jitter components from the PLL

synthesizer and from the system board. The 9DB202 has two PLL

bandwidth modes. In low bandwidth mode, the PLL loop bandwidth

is 500kHz. This setting offers the best jitter attenuation and is still

high enough to pass a triangular input spread spectrum profi le. In

high bandwidth mode, the PLL bandwidth is at 1MHz and allows

the PLL to pass more spread spectrum modulation.

For serdes which have x10 reference multipliers instead of x12.5

multipliers, each of the two PCI Express™ outputs (PCIEX0:1) can

be set for 125MHz instead of 100MHz by confi guring the appropriate

frequency select pins (FS0:1).

FEATURES

• Two 0.7V current mode differential HCSL output pairs

• One differential clock input

• CLK and nCLK supports the following input types:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum output frequency: 140MHz

• Input frequency range: 90MHz - 140MHz

• VCO range: 450MHz - 700MHz

• Output skew: 110ps (maximum)

• Cycle-to-cycle jitter: 110ps (maximum)

• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):

2.42ps (typical)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Available in lead-free RoHS compliant package

• Industrial temperature information available upon request

• For functional replacement use 8714004

9DB202属于集成电路（IC） > 应用特定时钟/定时。瑞萨科技有限公司制造生产的9DB202应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。