9DB1933集成电路（IC）的应用特定时钟/定时规格书PDF中文资料

General Description

The 9DB1933 zero-delay buffer supports PCIe Gen3

requirements, while being backwards compatible to PCIe Gen2

and Gen1. The 9DB1933 is driven by a differential SRC output

pair from an IDT 932S421, 932SQ420, or equivalent, main

clock generator. It attenuates jitter on the input clock and has a

selectable PLL bandwidth to maximize performance in systems

with or without Spread-Spectrum clocking.

Features/Benefits

• 8 Selectable SMBus Addresses/Mulitple devices can share

the same SMBus Segment

• 11 dedicated and 3 group OE# pins/Hardware control of the

outputs

• PLL or bypass mode/PLL can dejitter incoming clock

• Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL's

• Spread Spectrum Compatible/tracks spreading input clock

for low EMI

• SMBus Interface/unused outputs can be disabled

• Supports undriven differential outputs in Power Down mode

for power management