Description

Output Features

The ICS9DB102 zero-delay buffer supports PCI Express

clocking requirements. The ICS9DB102 is driven by a differential

SRC output pair from an ICS CK410/CK505-compliant main

clock. It attenuates jitter on the input clock and has a selectable

PLL Band Width to maximize performance in systems with or

without Spread-Spectrum clocking.

• 2 - 0.7V current mode differential output pairs (HCSL)

Key Specifications

• Cycle-to-cycle jitter < 35ps

• Output-to-output skew < 25ps

Features/Benefits

• CLKREQ# pin for outputs 1 and 4/output enable for Express

Card applications

• PLL or bypass mode/PLL can dejitter incoming clock

• Selectable PLL bandwidth/minimizes jitter peaking in

downstream PLL’s

• Spread Spectrum Compatible/tracks spreading input clock

for low EMI

• SMBus Interface/unused outputs can be disabled

• Industrial temperature range available

9DB102BGLFT属于集成电路（IC） > 应用特定时钟/定时。瑞萨科技有限公司制造生产的9DB102BGLFT应用特定时钟/定时专用时钟和计时 IC（集成电路）产品族中的产品主要用于执行与时间或频率信息生成和分配相关的各种操作，适合的设计环境较特定，例如 AMD 和 Intel 的中央处理单元 (CPU) 或图形处理单元 (GPU)、DVD 音频设备、蓝光光盘播放器、以太网设备、PCIe、SATA、光纤通道接口、车载娱乐总线等。