95V847YGLF-T中文资料瑞萨数据手册PDF规格书

Recommended Application:

• Zero Delay Board Fan Out, SO-DIMM

• Provides complete DDR registered DIMM solution

with ICSSSTV16857, ICSSSTV16859 or

ICSSSTV32852

Product Description/Features:

• Low skew, low jitter PLL clock driver

• 1 to 5 differential clock distribution (SSTL_2)

• Feedback pins for input to output synchronization

• Spread Spectrum tolerant inputs

Switching Characteristics:

• CYCLE - CYCLE jitter: <60ps

• OUTPUT - OUTPUT skew: <60ps

• Period jitter: ±30ps

• DUTY CYCLE: 49.5 - 50.5