950202中文资料Programmable Timing Control Hub™ For P4™数据手册Renesas规格书

描述 Description

The 950202 is a single chip clock solution for desktop designs using the Intel 845 chipset with PC133 or DDR memory. It provides all necessary clock signals for such a system. The 950202 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.

特性 Features

3 - Pairs of differential CPU clocks @ 3.3V
3 - 3V66 @ 3.3V
9 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - VCH/3V66 @ 3.3V, 48MHz or 66MHz
1 - REF @ 3.3V, 14.318MHz
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system malfunctions.
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write operations.
Uses external 14.318MHz crystal.
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps