VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

文件：361.5 Kbytes 页数：10 Pages

RENESAS

瑞萨

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

文件：310.32 Kbytes 页数：9 Pages

IDT

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

文件：310.32 Kbytes 页数：9 Pages

IDT

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

文件：361.5 Kbytes 页数：10 Pages

RENESAS

瑞萨

时钟发生器及支持产品 VIDEO GENERATOR CLK

Renesas

瑞萨

Package：8-SOIC（0.154"，3.90mm 宽）；包装：托盘 类别：集成电路（IC） 应用特定时钟/定时 描述：IC CLK FREQ GEN VID GENLOCK

Renesas Electronics America Inc

时钟发生器及支持产品 VIDEO GENERATOR CLK

Renesas

瑞萨

Package：8-SOIC（0.154"，3.90mm 宽）；包装：托盘 类别：集成电路（IC） 应用特定时钟/定时 描述：IC CLK FREQ GEN VID GENLOCK

Renesas Electronics America Inc