9170B-02CS08LF中文资料瑞萨数据手册PDF规格书

• On-chip Phase-Locked Loop for clocks synchronization.

• Synchronizes frequencies up to 107 MHz

(output) @ 5.0 V

• ±1ns skew (max) between input & output clocks @ 5.0 V

• Can recover poor duty cycle clocks

• CLK1 to CLK2 skew controlled to within ±1ns @

5.0 V

• 3.0 - 5.5 V supply range

• Low power CMOS technology

• Small 8-pin DIP or SOIC package

• On chip loop filter

• IDT9170B-01 for output clocks 20-107 MHz @ 5.0 V,

20 - 66.7 MHz @ 3.3 V

• IDT9170B-02 for output clocks 5-26.75 MHz @ 5.0 V,

5 - 16.7 MHz @ 3.3 V