2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

General Description The 8T73S208A-01 is a high-performance differential LVPECL clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T73S208A-01 is characterized to operate from a 2.5V and 3.3V powe

文件：878.66 Kbytes 页数：25 Pages

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One differential input reference clock

文件：441.69 Kbytes 页数：22 Pages

IDT

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

文件：438.6 Kbytes 页数：24 Pages

IDT

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

文件：438.6 Kbytes 页数：24 Pages

IDT

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

文件：438.6 Kbytes 页数：24 Pages

IDT

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

文件：438.6 Kbytes 页数：24 Pages

IDT

2.5V, 3.3V Differential LVPECL Clock Divider and Buffer

The 8T73S208A-01 is a high-performance differential LVPECL clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks.The 8T73S208A-01 is characterized to operate from a 2.5V and 3.3V power supply. Guaranteed output- ·One differential input reference clock\n·Differential pair can accept the following differential inputlevels: LVDS, LVPECL, CML\n·Integrated input termination resistors\n·Eight LVPECL outputs\n·Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8\n·Maximum input clock frequency: 1GHz\n·LVCMOS i;

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