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8T49N286A-DDDNLGI8中文资料瑞萨数据手册PDF规格书

8T49N286A-DDDNLGI8
厂商型号

8T49N286A-DDDNLGI8

功能描述

FemtoClock® NG Octal Universal Frequency Translator

文件大小

2.09596 Mbytes

页面数量

78

生产厂商 Renesas Technology Corp
企业简称

RENESAS瑞萨

中文名称

瑞萨科技有限公司官网

原厂标识
数据手册

下载地址一下载地址二到原厂下载

更新时间

2024-9-22 20:00:00

8T49N286A-DDDNLGI8规格书详情

Description

The 8T49N286 has two independent, fractional-feedback PLLs that

can be used as jitter attenuators and frequency translators. It is

equipped with six integer and two fractional output dividers, allowing

the generation of up to eight different output frequencies, ranging

from 8kHz to 1GHz. Four of these frequencies are completely

independent of each other and the inputs. The other four are related

frequencies. The eight outputs may select among LVPECL, LVDS,

HCSL or LVCMOS output levels.

This functionality makes it ideal to be used in any frequency

translation application, including 1G, 10G, 40G and 100G

Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T

G.709 (2009) FEC rates. The device may also behave as a frequency

synthesizer.

The 8T49N286 accepts up to four differential or single-ended input

clocks and a crystal input. Each of the two internal PLLs can lock to

different input clocks which may be of independent frequencies. The

other two input clocks are intended for redundant backup of the

primary clocks and must be related in frequency to their primary.

The device supports hitless reference switching between input

clocks. The device monitors all input clocks for Loss of Signal (LOS),

and generates an alarm when an input clock failure is detected.

Automatic and manual hitless reference switching options are

supported. LOS behavior can be set to support gapped or ungapped

clocks.

The 8T49N286 supports holdover for each PLL. The holdover has an

initial accuracy of ±50ppB from the point where the loss of all

applicable input reference(s) has been detected. It maintains a

historical average operating point for each PLL that may be returned

to in holdover at a limited phase slope.

The device places no constraints on input to output frequency

conversion, supporting all FEC rates, including the new revision of

ITU-T Recommendation G.709 (2009), most with 0ppm conversion

error.

Each PLL has a register-selectable loop bandwidth from 1.4Hz to

360Hz.

Each output supports individual phase delay settings to allow

output-output alignment.

The device supports Output Enable inputs and Lock, Holdover and

LOS status outputs.

The device is programmable through an I2C interface. It also supports

I

2C master capability to allow the register configuration to be read

from an external EEPROM. The user may select whether the

programming interface uses I2C protocols or SPI protocols, however

in SPI mode, read from the external EEPROM is not supported.

Features

• Supports SDH/SONET and Synchronous Ethernet clocks

including all FEC rate conversions

• <0.3ps RMS Typical Jitter (including spurs), 12kHz to 20MHz

• Operating modes: locked to input signal, holdover and free-run

• Initial holdover accuracy of ±50ppb

• Accepts up to four LVPECL, LVDS, LVHSTL, HCSL or LVCMOS

input clocks

• Accepts frequencies ranging from 8kHz up to 875MHz

• Auto and manual input clock selection with hitless switching

• Clock input monitoring, including support for gapped clocks

• Phase-Slope Limiting and Fully Hitless Switching options to

control output phase transients

• Operates from a 10MHz to 40MHz fundamental-mode crystal

• Generates 8 LVPECL / LVDS / HCSL or 16 LVCMOS output

clocks

• Output frequencies ranging from 8kHz up to 1.0GHz (diff)

• Output frequencies ranging from 8kHz to 250MHz (LVCMOS)

• Eight General Purpose I/O pins with optional support for status

and control

• Eight Output Enable control inputs

• Lock, Holdover and Loss-of-Signal status outputs

• Open-drain Interrupt pin

• Write-protect pin to prevent configuration registers being altered

• Nine programmable loop bandwidth settings for each PLL from

1.4Hz to 360Hz.

• Optional Fast Lock function

• Programmable output phase delays in steps as small as 16ps

• Register programmable through I2C / SPI or via external I2C

EEPROM

• Bypass clock paths for system tests

• Power supply modes:

VCC / VCCA / VCCO

3.3V / 3.3V / 3.3V

3.3V / 3.3V / 2.5V

3.3V / 3.3V / 1.8V (LVCMOS)

2.5V / 2.5V / 3.3V

2.5V / 2.5V / 2.5V

2.5V / 2.5V / 1.8V (LVCMOS)

• -40°C to 85°C ambient operating temperature

• Package: 72QFN, lead-free RoHs (6)

供应商 型号 品牌 批号 封装 库存 备注 价格
IDT
23+
NA/
6250
原装现货,当天可交货,原型号开票
询价
IDT
24+
QFN56
990000
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IDT
QFN56
608900
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IDT
23+
QFN56
8120
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IDT
2023+
QFN56
3000
一级代理优势现货,全新正品直营店
询价
IDT
23+
NA
246
原装正品代理渠道价格优势
询价
IDT
23+
QFN
10000
原包原标签100%进口原装常备现货!长期排单到货
询价
IDT
24+
QFN
18500
授权代理直销,原厂原装现货,假一罚十,特价销售
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IDT
22+
25000
原装现货,价格优惠,假一罚十
询价
IDT
22+
BGA
9600
原装现货,优势供应,支持实单!
询价