8T39S04A中文资料Crystal or Differential to Differential Clock Fanout Buffer数据手册Renesas规格书

描述 Description

The 8T39S04A is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock.The selected signal is distributed to four differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.

特性 Features

• Two differential reference clock input pairs
• Differential input pairs can accept the following input levels:LVPECL, LVDS, HCSL, HSTL and Single-ended
• Crystal Oscillator Interface
• Crystal input frequency range: 10MHz to 40MHz
• Maximum Output FrequencyLVPECL - 2GHzLVDS - 2GHzHCSL - 250MHzLVCMOS - 250MHz
• Two banks, each has two differential output pairs that can beconfigured as LVPECL or LVDS or HCSL
• One single-ended reference output with synchronous enable toavoid clock glitch
• Output skew: 80ps (maximum), Bank A and Bank B at the sameoutput level
• Part-to-part skew: 200ps (typical), design target
• Additive RMS phase jitter @ 156.25MHz, (12kHz - 20MHz):34.7fs (typical), 3.3V/ 3.3V
• Supply voltage modes:VDD/VDDO3.3V/3.3V3.3V/2.5V2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging

应用 Application

• 手持式超声扫描仪