Description

The 8SLVD1212 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of high-frequency,

very low additive phase-noise clock and data signals.

The 8SLVD1212 is characterized to operate from a 2.5V power

supply. Guaranteed output-to-output and part-to-part skew

characteristics make the device ideal for clock distribution

applications that demand well-defined performance and

repeatability.

Two selectable differential inputs and twelve low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the device inputs.

The 8SLVD1212 is optimized for low power consumption and low

additive phase noise.

Features

▪ Twelve low skew, low additive jitter LVDS output pairs

▪ Two selectable, differential clock input pairs

▪ Differential PCLK, nPCLK pairs can accept the following

differential input levels: LVDS, LVPECL, CML

▪ Maximum input clock frequency: 2GHz (maximum)

▪ LVCMOS/LVTTL interface levels for the control input select

pins

▪ Output skew: 40ps (maximum)

▪ Propagation delay: 310ps (typical)

▪ Low additive phase jitter, RMS; fREF = 156.25MHz,

10kHz to 20MHz: 77fs (typical)

▪ Device current consumption (IDD): 213mA (maximum)

▪ 2.5V supply voltage

▪ Lead-free (RoHS 6), 6 6 mm, 40-VFQFN packaging

▪ -40°C to 85°C ambient operating temperature

8SLVD1212ANLGI属于集成电路（IC） > 时钟缓冲器，驱动器。瑞萨科技有限公司制造生产的8SLVD1212ANLGI时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。