General Description

The 8S89874 is a high speed 1:2 Differential-to- LVPECL Buffer/

Divider. The 8S89874 has a selectable ÷1, ÷2, ÷4, ÷8, ÷16 output

divider, which allows the device to be used as either a 1:2 fanout

buffer or frequency divider. The clock input has internal termination

resistors, allowing it to interface with several differential signal types

while minimizing the number of required external components. The

device is packaged in a small, 3mm x 3mm VFQFN package, making

it ideal for use on space-constrained boards.

Features

• Two LVPECL/ECL output pairs

• Frequency divide select options: ÷1 (pass through), ÷2, ÷4, ÷8,

÷16

• IN, nIN input can accept the following differential input levels:

LVPECL, LVDS, CML

• Output frequency: 2GHz (maximum)

• Output skew: 15ps (maximum)

• Part-to-part skew: 250ps (maximum)

• Additive phase jitter, RMS: 0.20ps (typical)

• LVPECL supply voltage range: 2.375V to 3.63V

• ECL supply voltage range: -3.63V to -2.375V

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

8S89874属于集成电路（IC） > 时钟缓冲器，驱动器。瑞萨科技有限公司制造生产的8S89874时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。