8P34S1212集成电路（IC）的时钟缓冲器驱动器规格书PDF中文资料

Description

The 8P34S1212 is a high-performance differential LVDS fanout

buffer. The device is designed for the fanout of 1PPS signals or

high-frequency, very low additive phase-noise clock and data

signals. The 8P34S1212 is characterized to operate from a

1.8V or 2.5V power supply. Guaranteed output-to-output and

part-to-part skew characteristics make the 8P34S1212 ideal for

those clock distribution applications that demand well-defined

performance and repeatability.

Two selectable differential inputs and 12 low skew outputs are

available. The integrated bias voltage reference enables easy

interfacing of single-ended signals to the device inputs. The

device is optimized for low power consumption and low additive

phase noise.

Features

• 12 low skew, low additive jitter LVDS output pairs

• Two selectable, differential clock input pairs

• Differential CLK0, CLK1 pairs can accept the following

differential input levels: LVDS, CML

• Maximum input clock frequency: 1.5GHz (maximum)

• LVCMOS/LVTTL interface levels for the control input select pin

• Output skew: 10ps (typical)

• Propagation delay: 400ps (maximum)

• Low propagation delay variation across temperature for 1PPS

applications

• Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V,

12kHz– 20MHz: 34fs (typical)

• Maximum device current consumption (IDD): 185mA typ at 1.8V

or 200mA typ at 2.5V

• Full 1.8V or 2.5V supply voltage

• Lead-free (RoHS 6), 40-Lead VFQFPN packaging

• -40°C to +85°C ambient operating temperature

• Supports case temperature up to +105°C

• Supports PCI Express Gen 1-5