丝印：8P34S1106NLGI；Package：20-VFQFPN；1:6 LVDS Output 1.8V Fanout Buffer

Features • Six low skew, low additive jitter LVDS output pairs • One differential clock input pair • Differential CLK, nCLK pair can accept the following differential input levels: LVDS, CML • Maximum input clock frequency: 1.2GHz (maximum) • Output skew: 20ps (typical) • Propagation delay:

文件：1.2356 Mbytes 页数：17 Pages

RENESAS

瑞萨

丝印：8P34S1106NLGI；Package：20-VFQFPN；1:6 LVDS Output 1.8V Fanout Buffer

Features • Six low skew, low additive jitter LVDS output pairs • One differential clock input pair • Differential CLK, nCLK pair can accept the following differential input levels: LVDS, CML • Maximum input clock frequency: 1.2GHz (maximum) • Output skew: 20ps (typical) • Propagation delay:

文件：1.2356 Mbytes 页数：17 Pages

RENESAS

瑞萨

丝印：8P34S1106NLGI；Package：20-VFQFPN；1:6 LVDS Output 1.8V Fanout Buffer

Features • Six low skew, low additive jitter LVDS output pairs • One differential clock input pair • Differential CLK, nCLK pair can accept the following differential input levels: LVDS, CML • Maximum input clock frequency: 1.2GHz (maximum) • Output skew: 20ps (typical) • Propagation delay:

文件：1.2356 Mbytes 页数：17 Pages

RENESAS

瑞萨

丝印：8P34S1106NLGI；Package：20-VFQFPN；1:6 LVDS Output 1.8V Fanout Buffer

Features • Six low skew, low additive jitter LVDS output pairs • One differential clock input pair • Differential CLK, nCLK pair can accept the following differential input levels: LVDS, CML • Maximum input clock frequency: 1.2GHz (maximum) • Output skew: 20ps (typical) • Propagation delay:

文件：1.2356 Mbytes 页数：17 Pages

RENESAS

瑞萨