87973DYI-147LFT集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

特性 Features

• Fully integrated PLL

• Fourteen LVCMOS/LVTTL outputs to include: twelve clocks,

one feedback, one sync

• Selectable differential CLK, nCLK inputs or LVCMOS/LVTTL

reference clock inputs

• CLK0, CLK1 can accept the following input levels:

LVCMOS or LVTTL

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Output frequency range: 10MHz to 150MHz

• VCO range: 240MHz to 500MHz

• Output skew: 200ps (maximum)

• Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)

• Full 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Compatible with PowerPC™ and Pentium™ Microprocessors

• Available in lead-free packages

• For drop-in replacement use 87973i