8745BMI-21集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

特性 Features

• One differential LVDS output designed to meet

or exceed the requirements of ANSI TIA/EIA-644

One differential feedback output pair

• Differential CLK, nCLK input pair

• CLKx, nCLKx pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL

• Output frequency range: 31.25MHz to 700MHz

• Input frequency range: 31.25MHz to 700MHz

• VCO range: 250MHz to 700MHz

• External feedback for “zero delay” clock regeneration

with configurable frequencies

• Programmable dividers allow for the following output-to-input

frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8

• Cycle-to-cycle jitter: 30ps (maximum)

• Output skew: 40ps (maximum)

• Static phase offset: 25ps ± 125ps

• Full 3.3V supply voltage

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

• For functional replacement part use 8T49N285