丝印：87421AIL；Package：SOIC；÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

文件：408.84 Kbytes 页数：16 Pages

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丝印：87421AIL；Package：SOIC；÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

文件：408.84 Kbytes 页数：16 Pages

RENESAS

瑞萨

Package：8-SOIC（0.154"，3.90mm 宽）；包装：托盘 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLK GEN DIFF-LVDS 8-SOIC

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Package：8-SOIC（0.154"，3.90mm 宽）；包装：卷带（TR） 类别：集成电路（IC） 时钟发生器，PLL，频率合成器 描述：IC CLOCK GEN LVDS 8-SOIC

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