87421集成电路（IC）的时钟发生器PLL频率合成器规格书PDF中文资料

FEATURES

• One differential LVDS output

• One differential CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential input levels:

LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum clock input frequency: 1GHz

• Translates any single ended input signal (LVCMOS, LVTTL,

GTL) to LVDS levels with resistor bias on nCLK input

• Part-to-part skew: 500ps (maximum)

• Propagation delay: 1.7ns (maximum)

• Additive phase jitter, RMS @ 155.52MHz: 0.17ps (typical)

• Full 3.3V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package

• For functional replacement device use 87321